FPGA Emulation Engineer, up to Staff
Core
Develop and integrate large-scale SoC emulation platforms using Synopsys HAPS systems to verify complex SoC subsystems.
Role type
Senior IC FPGA Emulation Engineer
Builds
Large-scale SoC emulation platforms for chip verification
Domain
Semiconductor / SoC Design / FPGA Emulation
Required skills
SoC FPGA integration, Synopsys HAPS, FPGA architecture, synthesis, implementation, timing closure, AXI/AXI4/AXI-Lite, AHB, APB, Python, Tcl, Shell scripting, high-speed IO (DDR, MIPI, USB, PCIe), system-level debugging
Preferred skills
Multi-FPGA system integration, FPGA placement and routing, timing analysis, cross-functional collaboration, globally distributed environment experience
Technologies
Synopsys HAPS, Python, Tcl, Shell, AXI, AHB, APB, DDR, MIPI, USB, PCIe
Responsibilities
Build and integrate large scale SoC emulation platforms using multiple Synopsys HAPS systems; Optimize communication and data flow between internal subsystems on FPGA-mode; Develop and manage FPGA-mode clock and reset architecture; Collaborate with High-Speed IO designers to integrate FPGA high-speed IO models; Apply in-depth knowledge of FPGA architecture to maximize utilization and achieve timing closure; Debug and resolve integration issues across simulation, emulation, and software-validation environments.
Seniority
Senior, hands-on IC
