Sr. Staff/Principal PCIE Subsystem Architect
Core
Define and deliver high-performance I/O architectures for next-generation AI products in the datacenter, focusing on PCIe, CXL, UCIe, and NVMe standards.
Role type
Sr. Staff/Principal IC Subsystem Architect (High-Speed Interfaces)
Builds
Accelerator cards, server-class SoCs, and full-rack scale-up/scale-out deployments for datacenter AI products.
Domain
Datacenter, High-Speed Interfaces, AI Infrastructure
Deliverable
production ML models
Required skills
PCIe Gen6/Gen7 architecture, CXL, UCIe, NVMe, Ethernet, SR-IOV, RAS, telemetry, security, scale-up/scale-out design, SerDes/PAM4
Preferred skills
PCIe CEM standards, signal integrity, UALink/UAL, UEC, firmware/BIOS/UEFI requirements, IOMMU/SMMU, DMA, address translation
Technologies
PCIe, CXL, UCIe, NVMe, Ethernet, SR-IOV, PAM4, SerDes, PHY
Responsibilities
Define subsystem architecture from accelerator card through rack-level deployment; analyze PCIe ordering models, DMA flows, and link training; design error containment and recovery mechanisms; evaluate scale-up/scale-out architectures including switch fabrics and host-to-accelerator orchestration.
Seniority
Sr. Staff/Principal, hands-on IC
