Staff, Technical Standards – RISC-V SOC (Korea/Taiwan/Singapore/Japan Remote)
Core
Senior Technical Standards contributor focusing on RISC-V SOC, working with internal/external partners to develop, promote, and execute semiconductor industry standards while representing Qualcomm in standardization forums.
Role type
Senior IC Technical Standards Engineer (RISC-V SOC)
Builds
Industry technical standards for RISC-V SOC, processor architecture, and microarchitecture
Domain
Semiconductor industry, RISC-V architecture, SOC design
Required skills
RISC-V ISA, processor architecture, microarchitecture, memory architecture, standards body participation, consensus driving, SOC IP, bus, cache coherency, interrupt, system firmware, kernel knowledge, ASIC design, verification, networking, influencing
Preferred skills
Debug and Trace, Reliability Availability Serviceability, legacy architecture, processor core/system compliance certification, modeling and verification, physical design, government affairs, EDA, open-source licensing models, semiconductor development lifecycle, research and academic community networks, operating budgets, project financials, senior leadership interaction, technical leadership
Technologies
RISC-V, JEDEC, EDA, SOC IP, bus, cache coherency, interrupt, system firmware, kernel
Responsibilities
Understand semiconductor industry landscapes and competitor strengths/weaknesses, identify existing and emerging standards, develop and promote standards with external partners, formulate and execute Qualcomm's semiconductor standards strategy, file patents to protect novel IP aspects, represent Qualcomm as a delegate in standardization forums
Seniority
Senior, hands-on IC with strategic influence
