Staff System Modelling Engineer
Core
Lead the development of high-level SystemC/C++ models for Mix Signal IPs to support simulation, verification, and emulation of hardware and software components.
Role type
Staff System Modelling Engineer (Hardware/SoC)
Builds
Virtual models of connectivity IPs and virtual platforms for early software development and functional simulation.
Domain
Semiconductor / Hardware Engineering / SoC Design
Required skills
SystemC modelling, C/C++ programming, TLM 2.0, SCV, hardware/software design verification, SoC/ASIC modelling, emulation platform integration, technical leadership, process improvement
Preferred skills
Experience with Zebu, Palladium, Veloce emulation platforms, mentoring junior engineers
Technologies
SystemC, C++, C, TLM 2.0, SCV, Zebu, Palladium, Veloce
Responsibilities
Create virtual models of connectivity IPs using SystemC/C++ and C libraries; Test and debug models using SystemC simulation tools; Integrate models into emulation and verification environments; Work on Industry Emulation platforms such as Zebu, Palladium, Veloce; Integrate models into virtual platforms and verify functionality; Maintain and update models according to design changes; Document models and interfaces; Collaborate with stakeholders to ensure model quality; Contribute to modelling process improvements.
Seniority
Staff, hands-on IC with mentorship
