IP Design Verification Engineer
Core
Create DV infrastructure, integrate VIPs, execute test plans, debug failures, write assertions, and close code/functional coverage for Infra IP.
Role type
IP Design Verification Engineer
Builds
Infrastructure IP verification environments and testbenches
Domain
Semiconductor / Hardware Engineering / Digital Design
Required skills
System Verilog, UVM, Debug, Digital design concepts, DV methodologies, Test plan development, Coverage analysis, Monitor/Scoreboard/Sequencer design
Preferred skills
LPDRR/PCIe/CXL protocols, Scripting, Big test bench navigation
Technologies
System Verilog, UVM, VIPs
Responsibilities
Create DV infrastructure, Integrate VIPs, Create and execute test plans, Debug failures and write assertions, Ensure high quality verification, Work with stakeholders
Seniority
Mid-Senior (4+ years experience)
