Server CPU Clock Physical Design Engineer, Staff level - Cambridge, UK
Core
Define, implement, and optimize clock generation and distribution solutions for high-frequency, power-efficient data center CPU designs.
Role type
Staff IC CPU Clock Physical Design Engineer
Builds
Next-generation server-class CPU silicon
Domain
Semiconductor / CPU Physical Design
Required skills
Clock H-tree, Clock Mesh, Clock Spines methodologies, SPICE simulation, Static Timing Analysis (STA), Clock skew optimization, Power-aware clocking, Variation-aware implementation, EDA signoff flows, Cross-functional technical leadership
Preferred skills
Advanced process nodes (7nm and below), PLL specifications and jitter budgeting, Clock gating strategies, Multi-corner multi-mode timing closure, Scripting (TCL, Python, Perl)
Technologies
SPICE, EDA tools, Python, TCL, Perl
Responsibilities
Define clock generation and distribution methodology; Architect low-skew, low-power clock networks; Validate clock circuits via SPICE simulation; Debug timing, power, and noise issues; Mentor engineers and drive cross-functional methodology; Develop clock analysis and validation flows
Seniority
Staff, hands-on IC with technical leadership
