CareerPlan

CPU Server Physical Design Clock Engineer

Santa Clara, California, United States of AmericaFull-time$148k–$222k2026-09-22 → 2026-11-10

Core

Create best-in-class clocking solutions for next generation CPUs by working with microarchitecture, RTL, and physical design teams.

Role type

Senior IC physical design clock engineer

Builds

Next generation CPU chips

Domain

Semiconductor / CPU design

Required skills

Clock generation and distribution, H-tree/mesh/spines implementation, SPICE simulation, Device physics, RC delay analysis, Jitter analysis, Clock skew estimation

Preferred skills

Deep submicron process technology, PLL specifications, Standard cell optimizations, Clock methodology definition

Technologies

SPICE, CAD tools

Responsibilities

Perform jitter analysis and measurements, Implement and validate CPU clocking, Drive clock generation and distribution methodology, Optimize clocking for skew and power with CAD and block level designers

Seniority

Mid-Senior, hands-on IC