CPU Server Floorplan and Integration Engineer
Core
Design, floorplan, and integrate high-performance CPU designs for data center server solutions, meeting aggressive power, area, and performance goals.
Role type
Senior IC physical design engineer (CPU floorplan and integration)
Builds
Server-class high-performance CPU solutions
Domain
Semiconductor hardware design (CPU/SoC physical design)
Required skills
CPU floorplanning, block-level implementation, full chip integration, synthesis, place and route, signoff timing/power analysis, power grid planning, IP integration, static timing analysis (STA), electromigration and IR drop (EMIR) flows, low power design methodologies, circuit and layout design principles
Preferred skills
Deep submicron process technology nodes, leading physical design database development, industry standard tools for tapeout flows
Technologies
Synthesis, place and route, STA, EMIR flows, IP integration tools
Responsibilities
Perform CPU physical design tasks including floorplanning, Bump/RDL planning, IP integration, power/ground generation, and pin assignment; Oversee full chip floorplan, area optimizations, block partitioning, and pin assignments; Manage chip-level place and route and finalize the CPU database for construction and verification; Coordinate custom layout integration; Collaborate with external teams to fulfill IP technical and delivery requirements; Develop workflows for chip integration and analysis
Seniority
Senior, hands-on IC
