Data Center SoC Power & Limits Architect
Core
Define and drive next-generation power management, thermal, and system limits architecture for large-scale compute platforms (SOC, servers, racks, and cluster-level deployments) to enable maximum sustained performance within constrained power, cooling, and reliability envelopes.
Role type
Senior IC system architect (power & thermal limits)
Builds
End-to-end power and limits systems across silicon, platform, and data center infrastructure
Domain
Semiconductor / Data Center Infrastructure
Deliverable
production ML models
Required skills
Power management systems and limits control, Thermal and electrical constraints in high-performance systems, DVFS/DCVS and control systems, Data center/server architecture, Power delivery networks (VRs, PDN), Telemetry and system monitoring, System-level modeling and simulation
Preferred skills
MATLAB/Simulink, Python, ASIC design and verification
Technologies
MATLAB, Simulink, Python, BMC, EC, VRs, PDN
Responsibilities
Define holistic power, thermal, and electrical limits architecture across silicon, board, system, rack, and cluster levels; Architect power budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O; Develop strategies to maximize performance under datacenter-level constraints; Architect advanced dynamic power control systems (e.g., DVFS/DCVS, AVS-like systems) for fast transient response; Design closed-loop control systems using telemetry and feedback to optimize performance vs. constraints; Develop proactive and reactive limit management (thermal throttling, power capping, workload shaping); Define requirements and interfaces for telemetry infrastructure (sensors, BMC, firmware, system SW); Enable real-time monitoring and decision making across system layers; Ensure integration with platform controllers (e.g., BMC/EC, rack management, orchestration layers); Collaborate with silicon/SoC architects, platform teams, software/firmware teams, and data center infrastructure teams; Define hardware/software partitioning for limits enforcement with minimal overhead; Develop system-level models to predict performance vs. power/thermal constraints and evaluate algorithm and architecture trade-offs; Perform workload-driven analysis to validate architecture decisions; Drive innovations in power delivery efficiency, thermal-aware scheduling, AI workload-aware limits, and rack/cluster-level power orchestration.
Seniority
Senior, hands-on IC
