RTL Design(AI/ML) -Principal Engineer
Core
Developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon.
Role type
Principal RTL Design Engineer (Hardware)
Builds
Reusable IPs for SoC/subsystem integration
Domain
Semiconductor / Hardware Engineering
Required skills
RTL design (Verilog/SystemVerilog/VHDL), SoC/IP design and integration, Lint, CDC, synthesis, timing analysis, Low-power design techniques
Preferred skills
Full-cycle IP/SoC development, formal verification, low-power flows, post-silicon validation and bring-up
Technologies
Verilog, SystemVerilog, VHDL
Responsibilities
Work with architecture teams to define micro-architecture, Develop RTL based on micro-architectural specifications, Optimize designs for power, performance, and area, Perform design checks (Lint, CDC, synthesis, STA), Drive bug fixing and closure, Support design reviews and sign-off processes, Collaborate with verification teams on test plans and coverage closure
Seniority
Principal, hands-on IC
