Memory Control Design Engineer
Core
Design and deploy high-speed DDR memory controllers (1Ghz+) for Qualcomm's next-generation mobile products, interfacing with CPU, DSP, and multimedia processors.
Role type
Senior IC ASIC Design Engineer (Memory Controller)
Builds
High-speed LPDDR/PCDDR memory controller IP for mobile SoCs
Domain
Semiconductor / Mobile Computing / Memory Interface
Required skills
RTL design, DDR controller architecture, x86/ARM CPU/bus architecture, Synthesis, Timing Closure, Physical Design Support, Gate Level Simulation, Power Analysis, C/C++ modeling
Preferred skills
Debugging complex digital designs, Design methodology improvement
Technologies
LPDDR, PCDDR, RTL, C/C++, Synthesis tools, Timing Closure tools
Responsibilities
Develop design specifications and drive micro-architecture of logic design, Implement RTL and collaborate with verification engineers, Debug designs and provide support during integration, Perform synthesis, timing closure, physical design support, and power analysis, Contribute to C/C++ modeling of memory controller IP, Improve design methodology to drive productivity
Seniority
Mid-Senior, hands-on IC
