Sr. Staff PCIE Subsystem Architect
Core
Define and deliver high-performance I/O architectures for next-generation AI products in the datacenter, driving requirements from accelerator card through full-rack scale-up and scale-out deployments.
Role type
Sr. Staff IC PCIe Subsystem Architect
Builds
High-speed I/O subsystems for datacenter AI accelerators and server-class SoCs
Domain
Semiconductor / High-speed interfaces / Datacenter AI infrastructure
Deliverable
production ML models
Required skills
PCIe Gen6/Gen7 architecture, CXL, high-speed serial interface behavior, PCIe error containment and recovery (AER, DPC, FLR), I/O virtualization (SR-IOV, SIOV), RAS/telemetry/security, PCIe switch fabrics, NIC connectivity, rack-level deployment
Preferred skills
PCIe integrity/security/confidential-compute (IDE, DOE/SPDM, TDISP), PCIe CEM standards, UCIe/UALink/UEC ecosystems, firmware/BIOS/OS/driver requirements, high-speed SerDes/PAM4 PHY technologies, server SoC architectures (IOMMU/SMMU, DMA, address translation)
Technologies
PCIe, CXL, Ethernet, SR-IOV, SIOV, UCIe, UALink, UEC, SerDes, PAM4, IOMMU, SMMU
Responsibilities
Define subsystem architecture and drive requirements from accelerator card to rack scale; analyze PCIe ordering models, producer-consumer behavior, and ARM ordering; evaluate system-level tradeoffs for link training, latency, and error handling; design error containment and recovery mechanisms; specify I/O virtualization and isolation requirements; define RAS, telemetry, reliability, and security requirements; orchestrate host-to-accelerator connectivity and rack-level deployment; engage with cross-functional stakeholders to gather requirements and drive technical alignment
Seniority
Sr. Staff, hands-on IC with strategy & mentorship
