Design Verification Architect (Sr staff or above)
Core
Architect and overhaul the testbench environment for state-of-the-art interconnect IPs to verify complex designs.
Role type
Senior IC Design Verification Architect
Builds
Scalable, reusable DV environments for interconnect and subsystem designs
Domain
Semiconductor hardware engineering, interconnect IP, SystemVerilog/UVM
Required skills
UVM, SystemVerilog, UPF, digital design concepts, DV and power DV methodologies, bus protocols (AHB, AXI, ACE, CHI), ARM CPU/SoC architecture, multi-core CPU architecture, coherency protocols, virtualization, debugging
Preferred skills
Post-silicon bring-up, HW–SW debug, silicon debug toolchains
Technologies
SystemVerilog, UVM, UPF, ARMv8, AHB, AXI, ACE, CHI
Responsibilities
Drive testbench architecture and development for complex interconnect and subsystem designs, Ensure a scalable, reusable DV environment is built and deployable across different tiers of products, Work with all stakeholders to ensure program success
Seniority
Senior Staff, hands-on IC
