SMMU Senior Lead Design Verification Engineer
Core
Own the System Memory Management (SMMU) IP test bench and collaterals for next-generation System-on-chip (SoC) for smartphones and tablets.
Role type
Senior Lead Design Verification Engineer (Hardware/SoC)
Builds
System-on-chip (SoC) memory management units and validation infrastructure
Domain
Semiconductor / Hardware Engineering / SoC Design
Required skills
UVM, System Verilog, ARM bus protocols (AXI, AHB, APB, CHI), Virtual Memory concepts, SoC system architecture, Debugging, Analytical problem-solving
Preferred skills
Post-si bring-up, HW-SW debug, Silicon debug tool chains
Technologies
Certitude, VC Formal, Fishtail, UVM, System Verilog
Responsibilities
Develop test plans and test cases to cover design feature sets and achieve code/functional coverage closure; Debug regression signatures and identify bug fixes; Develop and deploy validation scripts/tools; Work with System Architects and Design teams on failure debugs; Analyze latency and bandwidth with SoC performance modeling teams; Debug and root cause post-silicon issues.
Seniority
Senior, hands-on IC
