3D Memory Chip Architect and Design, Principal Engineer
Core
Assess and optimize 3D Memory architectures for memory-centric compute systems to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency.
Role type
Principal 3D Memory Chip Architect and Design Engineer
Builds
3D DRAM/FLASH chips and near-memory computing architectures for data center, mobile, compute, and XR applications
Domain
Semiconductor / 3D Memory / Edge AI
Deliverable
production ML models
Required skills
3D integration, memory bank organization, signaling, bus design, IO design, compute fabrics, advanced packaging, power distribution topology, floorplanning, testability, repairability, EDA tools, Matlab, Python
Preferred skills
RTL design, circuit design, SoC architecture, DRAM/FLASH architecture performance assessment, memory circuit design, Verilog modeling, UCIe/UAL/LPDDR/HBM3/4/PCIe knowledge, mixed-signal design
Technologies
UCIe, UAL, LPDDR, HBM3, HBM4, PCIe, Verilog, Verilog-A, Verilog-AMS, Matlab, Python, EDA tools
Responsibilities
Develop and optimize 3D DRAM/FLASH organization and near-memory computing architectures; Develop and validate models for 3D Memory performance, power, and yield; Develop novel fabrics for high-bandwidth data distribution; Develop power distribution topology for robust memory operation; Simulate and emulate system performance of 3D memory architecture choices; Floorplan 3D memory chips and design memory array control structures
Seniority
Principal, hands-on IC
