System Performance Modeling Engineer
Core
Define and design platform infrastructure HW components (NoC, System Cache, Memory Controllers) using cycle-accurate and approximate models to support micro-architecture optimizations and system-level decisions.
Role type
Senior IC system performance modeling engineer (hardware architecture)
Builds
Next-generation SoC platform architectures and infrastructure IP components
Domain
Semiconductor / Hardware Architecture / System-on-Chip
Deliverable
production ML models
Required skills
Computer architecture, NoC topology, Memory hierarchy, C++, Python, Data Science, Machine Learning, Interconnect protocols (AHB/AXI/ACE), Performance/power analysis
Preferred skills
Master's or PhD in Microelectronics/CS, Mathematical background, NoC traffic engineering, Memory Controller protocols (LPDDR/DDR), ASIC design experience
Technologies
C++, Python, Cycle-accurate simulators, Approximate models, Machine Learning frameworks
Responsibilities
Participate in NoC and system memory architecture exploration campaigns; Drive architecture-oriented performance and power explorations; Develop new tools for architecture validation and exploration; Support exploratory methodology projects involving ML and data science; Expand and document innovative modeling frameworks.
Seniority
Mid-Senior, hands-on IC
