Director of Engineering for ML hardware design & Architecture
Core
Lead the definition and analysis of next-generation ML hardware accelerator architectures, specifically for vision applications in mobile and emerging products.
Role type
Director of Engineering, ML hardware design & Architecture
Builds
High-performance, power-efficient ML hardware accelerators for computer vision workloads
Domain
Semiconductor / Mobile SoC / Machine Learning Hardware
Deliverable
production ML models
Required skills
ML hardware accelerator architecture, SoC system development, VLSI design and verification, ML frameworks (TensorFlow Lite, ONNX), C/C++/SystemC programming, hardware simulation and profiling, bus/interconnect/memory technologies
Preferred skills
Vision-specific ML domain knowledge, global cross-functional collaboration, synthesis and physical design optimization, technical and people leadership
Technologies
Verilog, SystemVerilog, HLS, TensorFlow Lite, ONNX, SystemC, C++, C
Responsibilities
Architect high-performance, power-efficient ML hardware designs; Analyze and optimize hardware for PPA tradeoffs; Define hardware micro-architecture for ML algorithms; Lead HW IP development with RTL, verification, and synthesis teams; Collaborate with global hardware, software, and systems teams; Justify architectural decisions using models and real hardware; Invent and file patents for innovative solutions
Seniority
Director, strategic leadership with hands-on technical expertise
