CAD and PPA Methodology Engineer
Core
Develop new flows, methodologies, and algorithms to improve power, performance, and area (PPA) on state-of-the-art GPU cores.
Role type
Senior IC methodology engineer (GPU PPA)
Builds
GPU cores
Domain
Semiconductor / GPU Design
Required skills
RTL design, ASIC design flow, synthesis, static timing analysis, formal verification, physical design, ECO generation, Verilog, System-Verilog, design constraint management, clock tree analysis, EDA tools, script writing
Preferred skills
GPU core implementation, semi-custom design flow, flow improvement identification, RTL synthesis with physically aware tools, clock tree optimization, ECO methods, design goal tradeoffs
Technologies
Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower, PrimeTime, Prime Closure, UNIX shell, Python, Perl, TCL
Responsibilities
Collaborate with design, technology, power, implementation, sign-off, and post-silicon teams to drive PPA improvements; manage design goals and tradeoffs in power, performance, and area.
Seniority
Senior, hands-on IC
