Principal Engineer - HIG Component Validation
Core
Define architecture-aware validation strategies and coverage direction for future-generation High Bandwidth Memory (HBM) products, leading investigations from pre-silicon simulation through post-silicon characterization.
Role type
Principal Engineer - HBM Component Validation
Builds
Next-generation HBM memory products
Domain
Semiconductor / Memory / High Bandwidth Memory (HBM)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DRAM/HBM architecture expertise, pre-silicon and post-silicon debug, SPICE-level/timing-accurate simulation, Verilog/SystemVerilog, Python, Linux environments, version control (git/svn/Perforce), failure mechanism analysis, silicon data analysis, structured risk analysis
Preferred skills
HBM/advanced DRAM validation strategy definition, design-for-validation influence, validation hardware pathfinding (probe cards/sockets), high-speed I/O and signal-integrity validation, AI/ML in validation workflows
Technologies
Verilog, SystemVerilog, Python, SPICE, Linux, git, svn, Perforce
Responsibilities
Define architecture-aware validation strategies and coverage direction for future-generation HBM products; Drive validation readiness by preparing strategies, test environments, and execution plans before first silicon; Evaluate new DRAM/HBM architectural features and define validation requirements and testability needs; Develop validation strategies for new and high-risk product features; Leverage expert knowledge of DRAM and HBM architectures to define validation methodologies and identify risks early; Challenge design assumptions using silicon data, simulation results, and structured risk analysis; Use Verilog/SystemVerilog simulation to identify validation gaps early and evaluate coverage and observability pre-silicon
Seniority
Principal, strategy & mentorship
