Mixed-signal Design Architect, HBM Architecture
Core
Design, simulate, analyze, and optimize the architecture of 3D-stacked, high-performance memories for next-generation AI systems.
Role type
Senior IC mixed-signal design architect (HBM)
Builds
High-bandwidth memory products for emerging AI systems and applications
Domain
Semiconductor / Memory / AI Infrastructure
Deliverable
production ML models
Required skills
Analog and mixed-signal design, Transistor-level simulation (FineSim, HSPICE), Power delivery analysis, Architecture trade-off analysis, Thermal performance optimization, On/off-chip interface specification
Preferred skills
DRAM or 3D-stacked memory device experience, Thermal/power delivery solutions for stacked architectures, Scripting (Python, Perl), Hardware description languages (Verilog)
Technologies
FineSim, HSPICE, Python, Perl, Verilog
Responsibilities
Design, optimize, and simulate critical analog and/or mixed-signal circuits; Architect and design power delivery for high-performance, stacked memories; Analyze, specify, and prototype on-/off-chip interfaces; Perform timing, area, power, and complexity analysis; Define architectures for improved thermal management; Conduct pathfinding activities for future-generation stacked-memory products
Seniority
Senior, hands-on IC
