Senior Formal Verification Engineer - LPU
Core
Verify AI-related sophisticated ASIC designs and features using formal verification methods to ensure correctness and compliance with specifications.
Role type
Senior IC formal verification engineer (ASIC)
Builds
High-performance AI accelerators (GPUs/LPUs)
Domain
Semiconductor hardware design / AI computing
Deliverable
production ML models
Required skills
SystemVerilog Assertions (SVA), formal property verification, formal verification tools (JasperGold, VC Formal), scripting (Tcl, Python), ASIC verification methodologies
Preferred skills
Full-cycle formal sign-off experience, sequential equivalence checks, datapath verification, GPU/LPU architecture knowledge
Technologies
JasperGold, VC Formal, SystemVerilog, Tcl, Python
Responsibilities
Define verification scope and ensure correctness for ASIC designs; Employ formal techniques to acquire bounded proofs; Collaborate with architects and RTL teams to specify properties and resolve design issues; Develop and implement advanced formal verification environments and automated flows; Mentor junior engineers on formal techniques and processes; Support silicon bring-up and debug using formal methods.
Seniority
Senior, hands-on IC
