Member of Technical Staff (MTS) – HIG HBM Component Validation
Core
Technical leader and authority for validating advanced High Bandwidth Memory (HBM) products, defining validation coverage strategy, leading complex product debug, and driving a zero-escape validation mindset.
Role type
Senior IC HBM Component Validation Engineer
Builds
HBM product validation coverage, test programs, and debug solutions for memory semiconductor products
Domain
Semiconductor / Memory / HBM / DRAM
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DRAM and HBM architecture knowledge, circuit schematic debugging, timing-accurate circuit simulation, root-cause and electrical failure analysis, Python/C/C++ programming, Verilog/UVM simulation, ATE platform experience, algorithmic pattern generator (APG) concepts
Preferred skills
HBM or advanced DRAM validation coverage strategy definition, high-speed I/O and signal-integrity validation, lab equipment operation (oscilloscopes, logic analyzers), cross-functional team leadership across time zones
Technologies
Python, C, C++, Verilog, UVM, ATE platforms, version control systems
Responsibilities
Define validation methodologies and coverage plans for structural and functional test flows; lead root-cause analysis and electrical failure analysis of validation findings; guide development and validation of HBM test programs across ATE platforms; mentor engineers and provide technical training; apply AI/GenAI tools to accelerate coverage analysis and test code development
Seniority
Senior, hands-on IC
