Intern - Digital IP Design Engineer, DRAM
Core
Develop and validate digital IP circuits for next-generation DRAM products using RTL-to-GDS design methodologies.
Role type
Engineering Intern (Digital IP Design)
Builds
High-quality DRAM IPs for AI, mobile, client, data center, and graphics memory products
Domain
Semiconductor / Memory / Digital IC Design
Deliverable
production ML models | product features
Required skills
RTL-to-GDS design, SystemVerilog/UVM, Static Timing Analysis (STA), Python/Perl/TCL/MATLAB, Circuit analysis (PVT corners), Automation scripting
Preferred skills
Digital IC design/verification, RTL design/synthesis/timing closure, EDA tools, AI/Generative AI/Agentic AI workflows, Memory systems/VLSI development
Technologies
SystemVerilog, UVM, Python, Perl, TCL, MATLAB, EDA tools
Responsibilities
Support design, development, and verification of digital IP circuits; Perform circuit analysis across PVT corners; Develop automation scripts leveraging AI tools; Collaborate on design implementation and silicon validation; Present technical findings to leadership and customers
Seniority
Intern
