Principal Engineer, ASIC Analog Design
Core
Designing high-speed analog sub-blocks for advanced memory and storage PHYs in deep sub-micron nodes.
Role type
Principal Engineer, ASIC Analog Design
Builds
High-performance memory and storage solutions (DDR, LPDDR, GDDR, PCIe, etc.)
Domain
Semiconductor / Memory & Storage / Analog IC Design
Required skills
Analog/mixed-signal CMOS circuit design, High-Speed Memory Interfaces, SerDes Interfaces, PLL/DLL/CDR design, TX/RX Equalization, FinFET technologies, System-level modeling, ESD design, Lab testing, Power delivery circuits, Signal integrity analysis
Preferred skills
AI-enabled tools, Packaging and Board collaboration, Monte Carlo simulations
Technologies
Cadence ADE, Spectre, MATLAB, Calibre, Verilog-A, Python
Responsibilities
Own analog sub-blocks within the PHY and drive specification, design, simulation, and verification; Drive layout implementation through mask designers; Participate in silicon bring-up and characterization; Mentor junior engineers
Seniority
Principal, hands-on IC design with mentorship
