MTS – ASIC Silicon Debug, Device Technology & Yield Engineering
Core
Lead end-to-end investigation of silicon yield loss, field returns, and reliability failures for advanced ASIC devices, driving root-cause analysis across design, process, and test interactions.
Role type
Senior IC silicon debug and yield engineering lead
Builds
High-performance memory and storage ASICs (SRAM, PCIe PHY, SerDes, analog/mixed-signal)
Domain
Semiconductor manufacturing and ASIC design
Required skills
CMOS device physics, SRAM architecture, high-speed interface technologies (PCIe, ONFI, SerDes), post-silicon debug, failure analysis (FIB, SEM/TEM, EFA, OBIRCH, LVP, emission microscopy), signal integrity, power integrity, timing closure, yield data analysis, cross-functional technical leadership
Preferred skills
SSD controller/AI accelerator/networking ASIC experience, PCIe PHY/SerDes/memory subsystem debug, AI/ML tools for yield analytics and anomaly detection, mentoring engineering teams
Technologies
FIB, SEM, TEM, EFA, OBIRCH, LVP, emission microscopy, WAT, PCIe, ONFI, SerDes, SRAM, CMOS
Responsibilities
Lead root-cause investigations for silicon failures and yield excursions; Analyze device-level failure mechanisms and process sensitivities; Drive advanced failure analysis activities including physical cross-section analysis; Correlate failure signatures with design, process, and manufacturing data; Present complex technical findings to executive leadership; Influence design and technology roadmaps to improve future product robustness
Seniority
Senior, hands-on IC with cross-functional leadership