Sr. Staff SoC RTL Engineer
Core
Architect, design, and deliver digital hardware for ultra-low-power SoCs and MCUs powering wearables, medical devices, and edge AI applications.
Role type
Senior Staff SoC RTL Engineer (Individual Contributor)
Builds
Next-generation ultra-low-power semiconductor solutions (MCUs and SoCs)
Domain
Semiconductor / ASIC Design / Ultra-low-power Edge Computing
Deliverable
production ML models | product features
Required skills
Verilog, SystemVerilog, Microarchitecture design, ARM-based CPU subsystems, AMBA protocols (AHB, APB, AXI), ASIC front-end development (synthesis, timing, LINT, CDC, RDC), FPGA prototyping, Silicon bring-up, Low-power design techniques (clock gating, power management), IP integration
Preferred skills
ARM Cortex-M integration, MCU architecture, Memory controllers, DSPs, Hardware accelerators, UPF, Multi-voltage domains
Technologies
Verilog, SystemVerilog, ARM, AMBA, FPGA, UPF
Responsibilities
Define microarchitecture of digital SoC modules, Develop production-quality RTL, Own complex blocks from specification through pre-tapeout signoff, Integrate internal and third-party IP, Partner with verification and Physical Design teams, Mentor less-experienced engineers
Seniority
Senior Staff, hands-on IC
