Senior/Principal NAND Device Engineer
Core
Develop deep insight into NAND cell physics, variability, and reliability mechanisms to drive device–array co-optimization and next-generation NAND technology scaling.
Role type
Senior/Principal NAND Device Engineer (Device Technology Development)
Builds
Next-generation NAND memory products (3D NAND) for global deployment
Domain
Semiconductor / Non-volatile memory / Device Physics
Deliverable
production ML models
Required skills
NAND cell physics, electrical characterization, device–array co-optimization, statistical modeling, data analytics, Python, MATLAB, JMP, machine learning, automation frameworks, cross-functional collaboration
Preferred skills
Non-volatile memory experience, device variability/reliability mechanisms, memory array operation, algorithm development, AI/ML techniques, automated analysis pipelines
Technologies
Python, MATLAB, JMP, AI/ML frameworks, automation tools
Responsibilities
Analyze electrical characterization data to identify limitations; drive device–array co-optimization (Vt placement, sensing margins); translate device understanding into cell design and process optimization; apply AI/ML to extract insights from large-scale datasets; prototype novel device or algorithmic solutions; collaborate with process integration, cell design, and product engineering teams.
Seniority
Senior/Principal, hands-on IC with strategic influence