Design Infrastructure Engineer (Standard and Custom Cell Characterization)-HBM
Core
Build, enable, and scale characterization infrastructure for standard and custom cells to deliver generated IP for advanced memory and logic designs, specifically supporting High Bandwidth Memory (HBM) solutions.
Role type
Design Infrastructure Engineer (HBM/Cell Characterization)
Builds
Scalable characterization flows, Liberty models, and IP for HBM DRAM dies, logic dies, and 3D HBM architectures.
Domain
Semiconductor / Memory / Heterogeneous Integration (TSV)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CMOS digital and mixed-signal circuit design, device physics, PVT variation analysis, Liberty modeling (CCS/ECSM), SPICE-based simulation, Static Timing Analysis (STA), Python/Perl/Tcl scripting, SiliconSmart, PrimeLib
Preferred skills
Multi-technology process experience, HBM/DRAM/high-speed interface design, TSMC PDK familiarity, high-speed PHY design, TSV-aware design, Agentic AI workflow development
Technologies
TSV, TSMC, Micron internal nodes, Liberty, SPICE, STA, SiliconSmart, PrimeLib, Python, Perl, Tcl
Responsibilities
Develop scalable infrastructure for timing, power, noise, and signal integrity modeling; Build automated flows for multi-corner, multi-mode (MCMM) characterization and Liberty model generation; Enable characterization across heterogeneous processes (Micron internal and TSMC); Support diverse HBM product verticals including core dies and custom base dies; Integrate characterization flows into design/verification ecosystems; Lead debug and validation efforts by root-causing mismatches between SPICE, extracted views, STA, and silicon behavior.
Seniority
Mid-Senior, hands-on IC