Sr. Staff Engineer - Digital Design Verification
Core
End-to-end digital verification for complex Systems-on-Chip (SoCs) including CPUs, DSPs, security hardware, and interconnects for IoT and edge-compute applications.
Role type
Sr. Staff Engineer, Digital Design Verification
Builds
Production-ready silicon for low-power semiconductor solutions
Domain
Semiconductor / Low-power SoC design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, C/C++, constrained-random verification, scoreboarding, functional and code coverage, SoC verification, AMBA protocols, Python, Perl, Makefile
Preferred skills
ARM/RISC-V processor architectures, low-power digital architectures, security IPs, DSP subsystems, edge AI/ML workloads
Technologies
SystemVerilog, UVM, Verilog, C/C++, Python, Perl, Makefile, ARM, RISC-V, AMBA (AXI, AHB, APB)
Responsibilities
Own and execute end-to-end digital verification at block, sub-system, and full-chip levels; Architect and implement scalable UVM-based testbenches; Develop comprehensive test scenarios, stimulus, monitors, and checkers; Automate verification flows for regressions and coverage collection; Utilize advanced debugging methodologies to isolate and resolve complex issues; Collaborate with design teams to drive fixes and ensure verification quality.
Seniority
Sr. Staff, hands-on IC
