DRAM Design Technology Layout Engineer
Core
Translating schematics into layout for DRAM fabrication reticules and developing IP layouts for DRAM chips.
Role type
DRAM Design Technology Layout Engineer
Builds
Fabrication reticules and DRAM chip IP layouts
Domain
Semiconductor manufacturing / DRAM
Required skills
Advanced CMOS layout design, Physical verification (LVS/DRC/EM), Layout area and routing optimization, Design rule compliance, Yield and reliability analysis, Parasitic analysis, Electro-migration and IR-drop management, Cadence Virtuoso, Mentor Calibre, Schematic-to-layout collaboration
Preferred skills
Layout automation scripting, AI tool usage for design enhancement
Technologies
Cadence Virtuoso, Mentor Calibre
Responsibilities
Develop IP layouts for DRAM chips; Perform layout verification (LVS/DRC/EM) and quality checks; Deliver block-level layouts on time; Optimize layout for speed, capacitance, power, and area; Collaborate with global engineering teams; Plan and schedule layout projects.
Seniority
Mid-level, hands-on IC
