Senior Staff Digital Design Engineer
Core
Develop RTL designs using Verilog/SystemVerilog for digital IP blocks and subsystems, translating architectural specifications into clean, synthesizable RTL for data center and AI infrastructure.
Role type
Senior Staff Digital IC Design Engineer
Builds
Digital IP blocks and subsystems for connectivity, data center, and AI infrastructure
Domain
Semiconductor / Digital IC Design
Required skills
Verilog, SystemVerilog, RTL design, Linting, CDC, Low-power design, Timing analysis, Area optimization, Power optimization, Synthesis support, Debugging (simulation/emulation/FPGA/silicon), Mentorship
Preferred skills
Communication algorithms, DSP algorithms, UVM verification
Technologies
Verilog, SystemVerilog, UVM
Responsibilities
Develop RTL designs for digital IP blocks and subsystems; Translate architectural specifications into clean, synthesizable RTL; Perform linting, CDC and low-power design checks; Analyze timing, area, and power tradeoffs; Support synthesis and work with physical design teams on timing closure; Debug functional issues from simulation, emulation, FPGA prototyping or silicon bring-up; Mentor and coach new or less experienced team members.
Seniority
Senior Staff, hands-on IC with mentorship
