AMS Layout Engineer Intern - BS - 2027 Co-Op
Core
Implement physical design for high-speed analog and mixed-signal circuits for photonic transceivers and Electronic Integrated Circuits (EICs) in next-generation 100G+ optical link solutions.
Role type
AMS Layout Design Intern (Co-op)
Builds
Scalable, low-power, high-performance EICs for optical compute and interconnects
Domain
Semiconductor / Silicon Photonics / Analog & Mixed-Signal (AMS)
Deliverable
production ML models | product features
Required skills
CMOS digital electronics, Analog electronics, Python, Perl, DRC/LVS verification, Floor planning, Routing
Responsibilities
Design high-speed analog and mixed-signal layouts in advanced CMOS technology processes; Perform transistor level floor planning, routing, and verifying against design rules (DRC) and schematic connectivity (LVS); Work closely with Analog Circuit Design engineers to optimize layouts to meet performance requirements; Develop custom scripts to improve tools, flows, and methodologies used in the team's design environment.