Security Verification/Validation Engineer Intern, BS - Summer 2027
Core
Intern evaluating security verification tools and exploring AI assistance for the Security Development Lifecycle (SDL) in hardware and software security.
Role type
Intern, Security Verification/Validation Engineer
Builds
Security testing and validation for semiconductor products at RTL design phase
Domain
Semiconductor / Hardware Security
Required skills
Verilog, System Verilog, Unix scripting, security assurance principles, pre-silicon testing/debug, system architecture, AI prompting
Preferred skills
None stated
Technologies
Verilog, System Verilog, Unix, AI tools
Responsibilities
Evaluate specialized security verification tools from external suppliers; Explore scope for using AI assistance for facilitating security verification; Support Business Units to conduct product security testing on selected products at RTL design phase; Learn architecture/design and functional testing methodologies of the product and provide input on evolving existing strategy for expanding security specific coverage.
Seniority
Intern
