Analog IC Design Engineer, Intern
Core
Design integrated circuits for electrical and electro-optical interfaces at 100+ Gb/s using advanced technology nodes (3nm FinFET and 2nm GAAFET) for AI and Cloud data center applications.
Role type
Analog IC Design Intern (Industrial Master Thesis)
Builds
High-performance analog circuits and ICs for data infrastructure
Domain
Semiconductor / Analog IC Design / Data Center
Deliverable
production ML models | product features
Required skills
CMOS analog design, CMOS processes and fabrication, IC layout, CAD tools (Cadence)
Preferred skills
RF design techniques
Technologies
3nm FinFET, 2nm GAAFET, Cadence
Responsibilities
Design and simulate high performance analog circuits, learn advanced techniques in analog and high-speed layout, collaborate with team members
Seniority
Intern / Master Thesis Student
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