HSIO Test Solutions Engineering Lead
Core
Define test strategies and DFT architecture for next-generation HSIO silicon products, ensuring testability from architectural concept through high-volume manufacturing.
Role type
Senior IC Test Solutions Engineering Lead (HSIO/SerDes)
Builds
Production-ready silicon chips for data infrastructure (enterprise, cloud, AI, carrier)
Domain
Semiconductor / High-Speed I/O / Advanced Packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor Test Engineering, DFT, Silicon Validation, Yield Analysis, Cross-functional Leadership, Manufacturing Test Planning, SerDes Technologies, Die-to-Die Interfaces, Mixed-Signal Characterization
Preferred skills
Advanced Packaging, Chiplets, Heterogeneous Integration, AI/Networking Product Support, Python/Automation, Advantest 93K, Teradyne UltraFLEX
Technologies
PCIe, CXL, UCIe, SerDes (56G/112G/224G), ATE, Python
Responsibilities
Develop test strategies and DFT requirements for advanced HSIO technologies; Define and execute validation strategies for test chips and first-silicon bring-up; Develop production screening methodologies and manufacturing test plans; Lead cross-functional reviews and mentor engineers on next-generation test methodologies
Seniority
Senior, hands-on IC with leadership responsibilities
