IP Release Principal Engineer
Core
Senior technical individual contributor acting as the quality gatekeeper and first line of support for IP subsystem deliveries, ensuring RTL, synthesis, and DFT readiness for SoC integrators and external customers.
Role type
Senior IC IP Release Principal Engineer
Builds
Production-ready IP subsystem packages (RTL, constraints, DFT collateral) for SoC integration
Domain
Semiconductor, SoC architecture, Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (IP packages)
Required skills
RTL static analysis (Lint, CDC, RDC), Synthesis readiness validation, DFT enablement (scan, BIST, JTAG), IP delivery checklist execution, Version control and release packaging, Jira issue tracking, Perl/Python scripting
Preferred skills
SoC architecture and processor cores expertise, PCIE/CXL interface experience, Memory generation, Large design synthesis and timing closure, 2nm/3nm/5nm process nodes knowledge
Technologies
Lint, CDC/RDC checkers, Synthesis EDA tools, UPF, SDC, Jira, Perl, Python
Responsibilities
Own full RTL static analysis sign-off flow including Lint, CDC, and RDC checks; Drive front-end synthesis readiness and validate timing constraints; Ensure early DFT consideration and validate DFT handoff collateral; Execute IP delivery checklist at milestones and validate release packaging; Act as primary technical point of contact for triaging IP integration issues; Collaborate with TFM, SoC, DFT, and emulation teams on methodology and automation.
Seniority
Senior, hands-on IC
