Principal Analog Layout Engineer
Core
Designing layouts for High-Speed SerDes (HSS) IPs in deep sub-micron, FinFET technologies based on schematics from Circuit Design Engineers.
Role type
Principal Analog Layout Engineer
Builds
High-Speed SerDes (HSS) IPs for data infrastructure, Switch, Storage, and Optics applications
Domain
Semiconductor / Analog Mixed-Signal / High-Speed SerDes
Deliverable
production ML models | product features
Required skills
Analog layout design, DRC/LVS/ANT/ERC/EMIR analysis, Cadence Virtuoso VXL, Synopsys Custom Compiler, Mentor Graphics Calibre, deep sub-micron/FinFET process knowledge, schematic-to-layout translation
Preferred skills
None stated
Technologies
Cadence Virtuoso VXL, Synopsys Custom Compiler, Mentor Graphics Calibre
Responsibilities
Draw layouts for schematics created by Circuit Design Engineers using industry standard CAD tools in deep sub-micron, FinFET technologies; Communicate with Design Engineers to clarify and realize layout requirements based on schematic functions; Provide feedback to Circuit Design Engineers on modifications to schematics after layouts are completed; Interact with Physical Verification (PV) team to analyze DRC, LVS, ANT, ERC, and EMIR results and achieve PV closure
Seniority
Principal, hands-on IC