Forward Error Correction Intern
Core
Design and validate forward error correction (FEC) and DSP schemes for optical coherent transceivers implemented in hardware.
Role type
Intern, IC hardware/software engineer
Builds
Optical coherent transceiver hardware blocks (ASICs)
Domain
Semiconductor / Optical Communications
Deliverable
production ML models | product features | infrastructure
Required skills
Digital communication systems modeling, C/C++/Python/Verilog/SystemVerilog programming, System modeling
Preferred skills
Experience in error correcting schemes, Optimization problem solving
Technologies
C, C++, Python, Verilog, SystemVerilog
Responsibilities
Design optical communication-oriented DSP/FEC algorithms, Validate FEC/DSP schemes, Design digital implementation architectures, Develop software for communications system simulation
Seniority
Intern
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