Sr. Staff RTL Design Engineer - PCIe
Core
Define micro architecture and implement RTL for PCIe/CXL subsystems in high-performance data processing silicon.
Role type
Sr. Staff RTL Design Engineer (PCIe/CXL)
Builds
Custom ASICs for Cloud AI, Enterprise, and Carrier compute platforms
Domain
Semiconductor / Data Infrastructure / High-speed Interconnects
Deliverable
production ML models | product features
Required skills
SystemVerilog, Verilog, PCIe protocol architecture, CXL.io/CXL.cache/CXL.mem, ARM SoC integration, AMBA protocols, Clocking/Resets/CDC, EDA tools, Tcl/Perl/Python scripting
Preferred skills
Mentorship, design quality improvement, cross-functional technical leadership
Technologies
SystemVerilog, Verilog, Synopsys, Cadence, Mentor/Siemens, GIT, SVN
Responsibilities
Own PCIe/CXL subsystem micro architecture definition and RTL implementation; Collaborate with Architecture teams to translate requirements into robust designs; Work with Design Verification teams on test-plan reviews and coverage closure; Partner with Physical Design and DFT teams; Support silicon bring-up and post-silicon debug; Drive design quality improvements and coding best practices; Mentor junior designers
Seniority
Sr. Staff, hands-on IC with technical leadership
