Principal Engineer, Subsystem CoE Emulation
Core
Lead emulation of key subsystems (Boot, Security, High-speed interfaces, Memory, Peripherals) for advanced SoCs to enable pre-silicon validation and software readiness.
Role type
Principal Engineer, Subsystem CoE Emulation
Builds
Scalable emulation infrastructure and pre-silicon validation environments for Custom Compute and Storage SoCs.
Domain
Semiconductor, SoC Design, Hardware Emulation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC emulation and validation, High-speed protocol expertise (PCIe, CXL, Ethernet), Memory interface expertise (DDR, HBM), Peripheral interface expertise (SPI, I2C, UART, USB), Emulation platform proficiency (Palladium, ZeBu, Veloce), HW/SW boundary debugging, Scripting (Python, Perl, Tcl, Shell), Cross-functional leadership
Preferred skills
None explicitly stated as preferred
Technologies
Palladium, ZeBu, Veloce, Synopsys, Cadence, Siemens, Python, Perl, Tcl, Shell
Responsibilities
Lead development of complex SoC emulation models including design integration and environment setup; Drive emulation bring-up activities including clock/reset sequencing and firmware boot; Create and execute emulation test plans for verification and performance analysis; Collaborate with RTL, verification, and firmware teams to define requirements and develop hardware models; Debug complex SoC and subsystem issues across RTL, firmware, and toolchain; Optimize emulation performance via model partitioning and timing analysis; Automate flows and improve productivity through scripting; Interface with EDA vendors to evaluate capabilities and resolve technical issues; Define and execute emulation strategy for complex SoCs across multiple subsystems.
Seniority
Principal, hands-on IC with strategic leadership
