Emulation Lead, Senior Principal Engineer
Core
Define and drive emulation strategy for complex connectivity silicon (ODSP, PCIe/CXL retimers, Ethernet PHYs, AEC/AOC) to ensure high-quality tape-out and efficient validation.
Role type
Senior Principal Engineer, Connectivity Emulation Lead
Builds
Pre-silicon and post-silicon validation environments for high-speed connectivity devices
Domain
Semiconductor / High-speed connectivity / SoC emulation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC emulation platforms (Palladium, Veloce, Zebu), FPGA prototyping, Verilog/SystemVerilog, test planning, simulation, debug, SoC development flows, system-level validation, Python, Perl, Tcl, UNIX shell scripting, automation
Preferred skills
Networking device emulation, mixed-signal designs, PHY/Layer-2/3 functionality, firmware/software bring-up, scaling emulation infrastructure
Technologies
Palladium, Veloce, Zebu, Verilog, SystemVerilog, Python, Perl, Tcl, UNIX shell
Responsibilities
Define and execute emulation strategies and test plans for complex connectivity silicon; Work with project leadership to define emulation hardware and software requirements; Collaborate with EDA and emulation hardware vendors to enable new platforms and drive debug; Develop HW/SW enablement flows and tools to accelerate RTL validation; Interface with pre-silicon and post-silicon teams to optimize validation methodologies; Build and maintain automation flows and infrastructure to improve productivity
Seniority
Senior Principal, hands-on IC leadership
