Formal Verification Engineer - Professional Level
Core
Own formal verification deliverables end-to-end for RTL blocks, producing sign-off artifacts and preventing regressions.
Role type
Professional IC formal verification engineer
Builds
Formal verification environments and proof closure for RTL blocks
Domain
Semiconductor hardware design / RTL verification
Required skills
SVA, formal tools (Jasper, VCF, Questa Formal/Onespin), RTL debugging, requirement clarification, verification strategy definition
Preferred skills
Experience with caches, pipelined processors, DMAs, NoCs
Technologies
SVA, Jasper, VCF, Questa Formal, Onespin
Responsibilities
Clarify requirements and co-define verification strategy, produce maintainable SVA and clean formal environments, debug efficiently and partner with designers on fixes, keep stakeholders aligned with updates and evidence
Seniority
Professional, hands-on IC
