External Manufacturing Staff Operation Engineer
Core
Own and maintain wafer bumping processes to achieve yield, quality, cycle time, and cost targets for high-volume semiconductor production.
Role type
Senior IC process engineer (wafer bumping & advanced packaging)
Builds
Wafer bumping and DPS (Die-to-Panel/Substrate) processes for high-volume semiconductor manufacturing
Domain
Semiconductor manufacturing / Advanced packaging
Required skills
Wafer bumping process optimization, DOE design, root cause analysis, failure analysis, SPC monitoring, material qualification, continuous improvement, technical training
Preferred skills
UBM deposition, photolithography, electroplating, reflow, wet etch, wafer thinning, solder bump technology, Cu pillar bumping, WLCSP, JMP/Minitab statistical analysis
Technologies
JMP, Minitab, SPC tools, FMEA, 8D, Control Plan
Responsibilities
Conduct DOE and process characterization for new products and materials; Perform root cause analysis and implement corrective actions for yield and defectivity issues; Lead failure analysis for bump defects (missing bump, bridging, voids, delamination); Establish SPC monitoring and process control plans; Evaluate and qualify new materials, masks, tooling, and equipment; Provide technical training to process technicians.
Seniority
Senior, hands-on IC
