Senior Digital IP Design Manager
Core
Manage the design of digital datapath and subsystem IP for next-generation CMOS image sensors and the onsemi Treo platform.
Role type
Senior IC digital IP design manager
Builds
Digital datapath IP and modules for CMOS image sensors; core platform digital-on-top and subsystem IP for the onsemi Treo platform
Domain
Automotive semiconductor / CMOS image sensors
Deliverable
production ML models | product features | infrastructure
Required skills
Digital IC design, Digital IP or SoC development, Automotive IP, RTL design (SystemVerilog/Verilog), Low-power design, IP reuse and configurability, Cross-functional technical leadership
Preferred skills
CMOS image sensor digital pipelines, Platform or subsystem-level IP development, Functional safety concepts, EDA automation/scripting/AI-assisted workflows, Scaling or building new teams
Technologies
SystemVerilog, Verilog
Responsibilities
Lead the design of digital datapath IP and modules for CMOS image sensors; Drive development of core platform digital-on-top and subsystem IP for the onsemi Treo platform; Ensure IP meets automotive quality, safety, and reliability requirements; Partner with architecture, DV, PD, analog, mixed-signal, system, full-chip integration, firmware, and software teams; Provide technical guidance on RTL quality, low-power design, clocking/reset strategies, and design-for-test; Lead and mentor talented digital IP designers; Stay engaged with emerging trends, especially AI/ML-driven approaches to RTL generation, integration, Si debug, and design-space exploration
