Sr Principal Analog Design Engineer
Core
Architecting, designing, and delivering production-proven analog IP blocks for power management, clock generation, and error management subsystems within the onsemi Treo™ SoC platform.
Role type
Sr Principal Analog Design Engineer (IC/SoC)
Builds
Scalable, safety-focused power, clock, and system management IP for automotive and industrial SoCs
Domain
Semiconductor / Analog IC Design / Automotive Electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog IP architecture, Power management circuit design, Clock generation and distribution (PLLs, oscillators), Functional safety (ISO 26262), Mixed-signal SoC integration, Schematic capture, Simulation planning, Layout collaboration, Silicon validation, Debug and failure analysis, Device physics, PVT and reliability analysis
Preferred skills
ISO 26262 work product development, Safety diagnostics and fault-injection concepts, Mixed-signal verification, Post-silicon debug, Platform-level IP reuse strategies
Technologies
Treo™ platform, SoC integration flows, Automotive-grade design tools
Responsibilities
Architect and deliver analog IP blocks for power, clock, and error management; Drive designs from concept through silicon validation; Act as design quality reviewer for schematics, simulations, and layouts; Mentor junior and mid-level analog engineers; Collaborate with digital design, verification, and physical design teams; Apply functional safety concepts (ISO 26262) at the IP level
Seniority
Sr Principal, hands-on IC design with technical leadership