Design Verification Engineer | Sensing
Core
Develop and execute verification plans and SystemVerilog testcases for advanced mixed-signal sensor circuits and high-performance digital circuits interfacing with analog circuitry.
Role type
Senior IC design verification engineer (mixed-signal/AMS)
Builds
Next-generation mixed-signal chips for sensing applications
Domain
Semiconductor / Mixed-signal analog and digital integrated circuits
Deliverable
production ML models | product features
Required skills
SystemVerilog, mixed-signal chip verification, digital/analog verification, verification plan development, behavioral modeling, regression testing, design for testability (DFT), risk assessment
Preferred skills
Code and functional coverage metrics, constrained random verification, Cadence simulation tools, UART/SPI/I2C protocols
Technologies
SystemVerilog, Cadence, DFT methodologies
Responsibilities
Develop detailed verification/test plans covering digital/analog functionality; Develop SystemVerilog chip-level testcases; Perform simulation, debug, and verification closure; Identify design bugs and ensure robustness; Create behavioral models for analog blocks; Execute regression tests; Collaborate with design teams to close spec gaps; Drive verification flow improvements.
Seniority
Senior, hands-on IC
