Senior Staff RTL Design /Verification
Core
Senior Staff RTL Design/Verification engineer developing high-complexity Control and Management (CnM) IPs for switching System-on-Chip (SoC) devices used in AI and cloud data centers.
Role type
Senior Staff IC RTL Design/Verification Engineer
Builds
High-complexity Control and Management (CnM) IPs for switching SoCs
Domain
Semiconductor / Data Infrastructure / AI & Cloud
Deliverable
production ML models | product features | infrastructure
Required skills
RTL frontend design, verification, IP development, micro-architecture, digital logic, CDC/RDC, SystemVerilog, UVM methodology, system-level design
Preferred skills
Mentoring talent, driving innovative solutions for design and micro-arch challenges, post-silicon debug support
Technologies
SystemVerilog, UVM
Responsibilities
Develop best-in-class high-complexity CnM IPs for switching chips, ensure IPs meet functional/performance/power/quality requirements, engage with SW/FW and Architecture teams, support post-silicon debug and root-cause analysis
Seniority
Senior Staff, hands-on IC
