Design Verification Engineer
Core
Design Verification Engineer building DV environments and functional models for next-generation automotive connectivity IP solutions.
Role type
Design Verification Engineer
Builds
Low-power BLE and UWB IP blocks for automotive applications
Domain
Automotive connectivity, Ultra-Wideband (UWB), Bluetooth Low Energy (BLE)
Required skills
Verilog, SystemVerilog, VHDL, UVM, BFM creation, test plan creation, CDC/RDC fundamentals, constrained random verification, formal verification
Preferred skills
CPF/UPF low-power verification, AHB/APB bus protocols
Technologies
Verilog, SystemVerilog, VHDL, UVM
Responsibilities
Building DV environments from scratch, coding block functional models (BFM), creating and executing test plans
Seniority
Mid-level IC (2–5 years experience)
