Lead Engineer – RTL Design (Wireless Modem IP)
Core
Design and develop high-performance, power-efficient RTL for wireless modem IPs enabling Wi-Fi and low-power IoT devices, focusing on digital baseband and PHY-layer signal processing.
Role type
Senior IC RTL Design Engineer (Wireless Modem IP)
Builds
Digital baseband and PHY-layer IPs for Wi-Fi and IoT wireless connectivity
Domain
Semiconductor / Wireless Communications / Digital Signal Processing
Required skills
Verilog/SystemVerilog, Digital Microarchitecture, Synthesis, DSP block design (FIR, FFT, Correlators, FEC), PPA optimization, Testbench development, CDC/RDC analysis
Preferred skills
IEEE 802.11 Wi-Fi, 4G/5G cellular, OFDM systems, Low-power RTL design, SoC integration
Technologies
Verilog, SystemVerilog, FIR filters, FFT, Correlators, FEC decoders
Responsibilities
Design synthesizable RTL for baseband and PHY blocks; Define microarchitecture and implement DSP modules; Optimize designs for PPA; Develop testbenches and execute verification plans; Perform design quality checks (Lint, CDC, RDC); Collaborate on IP integration and cross-functional debugging
Seniority
Senior, hands-on IC
