Associate Staff Modem Verification Engineer
Core
Own verification of wireless modem IP, subsystems, and SoCs, focusing on PHY/MAC functionality, datapaths, control, and digital/RF interfaces.
Role type
Senior IC design verification engineer (wireless modem)
Builds
Robust wireless modem IP and SoC solutions for smart home, industrial IoT, and smart cities markets
Domain
Semiconductor / Wireless Connectivity / SoC Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random verification, SVA, functional coverage, regression management, RTL debugging, C/C++, Python/Tcl/Shell scripting
Preferred skills
Wi-Fi/BLE/Zigbee/Thread/Matter protocols, DSP fundamentals, MATLAB/Simulink, gate-level simulation, timing debug (SDF), CDC/RDC analysis, UPF, formal verification, emulation, FPGA prototyping, CI/CD workflows
Technologies
SystemVerilog, UVM, Verdi, DVE, SimVision, VCS, Xcelium, Questa, Python, Tcl, Shell, Git, Jenkins
Responsibilities
Develop and execute verification plans with coverage and sign-off criteria; Build and maintain reusable SystemVerilog/UVM environments; Create directed and constrained-random tests for coverage closure; Verify modem datapaths, PHY/MAC, and digital/RF interfaces; Debug RTL and gate-level regressions; Collaborate with cross-functional global teams; Drive features from spec review to sign-off; Improve verification automation and infrastructure; Mentor junior engineers
Seniority
Senior, hands-on IC
